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SystemVerilog Assertions Handbook, 4th Edition: ... for Dynamic and Formal Verification By Ben Cohen, Srinivasan Venkataramanan, Ajeetha
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- Sales Rank: #857419 in Books
- Published on: 2015-10-15
- Original language: English
- Number of items: 1
- Dimensions: 11.00" h x .93" w x 8.50" l, 2.08 pounds
- Binding: Paperback
- 410 pages
About the Author
This SVA 4th Edition evolved from many years of practical experiences, training, and studies in the processes / design / verification / and language worlds. This book is an excellent reference in the process and application of SVA. It was created by four authors who came from very strong technical backgrounds, thus putting a lot of synergy in the creation of this book. Ben has many years of design, synthesis, and verification of digital designs; he authored 12 books on VHDL, Verilog, design processes, VMM, PSL, and SVA, and has taught several classes in these fields. Srini worked at Intel as a verification engineer, and at Synopsys as an application and verification field engineer; he is now CTO of CVC Pvt Ltd, a high-end design-verification consulting company, and provides training in SV, SVA, VMM, OVM/UVM, VHDL, consulting for companies, and sales representation for many EDA products. Ajeetha has many years of experience in design and verification using VHDL, SV, SVA, VMM, OVM/UVM; she is the founder, CEO and Managing Director of CVC. She has also been consultant for many EDA companies and verification turnkey projects across India, Israel & Taiwan. Lisa worked at Cadence as a methodology and product engineer supporting assertions in simulation, formal verification, and emulation. She participated in the SVA standardization work for the IEEE 1800-2009 release. She also managed an organization that was responsible for the definition, verification, and support of Telecom IC's, LAN IC's, and ATM IC's at Lucent Microelectronics. She now is a technical marketing manager at Real Intent.
SystemVerilog Assertions Handbook, 4th Edition: ... for Dynamic and Formal Verification
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